The present invention relates generally to the timing of integrated circuit designs, and more specifically to a delay circuit that generates a delay equal to a percentage of an input pulse width.
In semiconductor circuit design, it is desirable to generate different timing in circuits in order to control operations of an integrated circuit chip. For example, it may be desirable to generate a timing that occurs at a specific phase of a clock cycle or that is related to the delay of another circuit timing. Some circuit designs generate timings by using simple delays that buffer signals to generate a delay. These simple delay techniques have a lot of sensitivities and variations to Process, Voltage and Temperature (P-V-T) conditions that a circuit design may experience. However, these techniques do not track to a reference delay or cycle, so are not useful for placing timings at a specific percentage of a reference time. Another delay technique that solves this issue is to create a delay that tracks to a reference clock by using a delay-locked-loop (DLL) device or a phase-locked-loop (PLL) device. In such approaches, a delay chain or ring oscillator is controlled by a DLL device or a PLL device and varied until there is a total delay that matches the reference clock. As an example, it may be desirable to generate a signal that is at 270 degrees of the reference clock. A DLL device or PLL device can be used to lock to the reference clock and then produce an output at the desired phase of the cycle. This is typically accomplished in a DLL device by having multiple output points along the delay line that represent different percentages of the total cycle time. Timing circuits that employ a DLL device or a PLL device are typically very complex, require many clock cycles to lock, and occupy a large amount of space on an integrated circuit chip, increasing cost.